Thanks John, i got the point.
Actually i am using Olimex Can Board driver. And for that it is
with sampling rate of 87.5 %.
if we consider Transreceiver delay = 0. Right ?
cable cost is increasing the budget.
Post by raj katoch**
That app node from freescale is one of the better ones out there
detailing how the Tq are derived and what is needed to calculate them.
However, they tend to work the numbers backwards from the way you would
intuitively do it hence the confusion. Normally what I do is select how
many Tq per bit I want and then pick a prescaler that will give me that for
the desired bit rate. And I want to be able to select a sample point at
75% to 85% of a bit time (after Phase_seg1)..
Following their logic that they want the Tprop_seg to be equal to 2x bus
propagation delay so their approach actually makes a lot of sense.
For example 1.
They want 500ns Tprop_seg and they need a Tq period that can do this with
a multiple of 8 or less. So we get 5, 4, 2 and 1 that will divide into
500nS without a remainder (100ns, 125ns, 250ns and 500ns) . Since the MPU
clock is 8MHz we need to be able to divide that to create one of those
periods without a remainder to create the CAN clock.
And we need to keep in mind that our bit rate will be 1Mbps so we need
an integral number of CAN clock periods to create our 1uS bit time.
Clearly 500ns is out as is 250nS since that gives us only 4 Tq which is
below the minimum # of Tq. That leaves 100ns or 125ns for a Tq count of 8
or 10 both of which could be used except we can't create a 100ns Tq from
8MHz.
So Step 2, as described on page 9 is to create a CAN clock frequency that
can be generated by dividing the system clock with an integer and also
gives a CAN clock period that can be an integer multiple of the bit rate.
Therefore in example 1, the 1000 is the number of nano seconds for a
single bit at 1 Mbps.
For example 2.
With a 125k bit rate the number of nanoseconds that make up 1 bit is 8000
or 8uS. The Tprop-seg needs to be 800nS in this example. Once again we
can create a number of different CAN clock rates from the 8Mhz MPU clock.
Dividing by 2 results in 32 Tq and that's too large. Dividing by 3 creates
a non integer clock rate. Dividing by 4 gives us 2Mhz with a clock period
of 500nS and that goes into the 125kbps bit period of 8uS 16 times.
That's the starting point. And we can create a Tprop_seg from 2x 500nS
that is larger than the needed 800nS. Finally the calculations show how to
determine the RJW (SJW) and since they have the rule for selecting
Tphase_seg1 they end up recalculating with a 1MHz CAN clock and 8 Tq per
bit and they sample at 62.5% of a bit time.
John Dammeyer
*"ELS! The Solution"
*Automation Artisans Inc.
http://www.autoartisans.com/ELS/
Ph. 1 250 544 4950
-----Original Message-----
*Sent:* Sunday, July 15, 2012 5:41 AM
*To:* Canlist
*Subject:* [CANLIST] Calculating - Time Quanta per bit
Hi,
I am going through following application note from freescale AN1798.
http://cache.freescale.com/files/microcontrollers/doc/app_note/AN1798.pdf
I am not getting one point, in this application note how, *Time Quanta
per bit* is calculated ?
*Example-1 *on Page 10* :--*
Step 2: A prescaler value of 1 gives a CAN system clock of 8MHz and
a Time Quantum of 125ns. This will give *1000 */ 125 = 8 time
quanta per bit.
*Example-2 *on Page 12* :--*
Step 2: A prescaler value of 4 gives a CAN system clock of 2MHz and
a Time Quantum of 500ns. This will give *8000 */ 500 = 16 time
quanta per bit.
Here in both the above examples from where quantity *1000 & 8000* are
coming from ?
Please suggest,
Thanks & Regards,
Katoch